|Detailed Description||:||SDRAM Memory IC 64Mb (4M x 16) Parallel 166MHz 5ns 54-TSOP II|
|Mounting Type||:||Surface Mount|
|Supplier Device Package||:||54-TSOP II|
|Operating Temperature||:||-40?C ~ 85?C (TA)|
|Memory Size||:||64Mb (4M x 16)|
|Voltage – Supply||:||3V ~ 3.6V|
|Package / Case||:||54-TSOP (0.400″, 10.16mm Width)|
54.00 AED – 90.00 AED
|Manufacturer Part No:||W9864G6JH-6I|
|Enrgtech Part No:||ET16500158|
|Product Range:||PolySwitch RXEF Series|
pack of 3, pack of 5
36.00 AED – 120.00 AED
The SN65175 and SN75175 are monolithic quadruple differential line receivers with 3-state outputs. They are designed to meet the requirements of ANSI Standards EIA/TIA-422-B, RS-423-B, and RS-485, and several ITU recommendations. These standards are for balanced multipoint bus transmission at rates up to 10megabits per second. Each of the two pairs of receivers has a common active-high enable. The receivers feature high input impedance, input hysteresis for increased noise immunity, and input sensitivity of ?200 mV over a common-mode input voltage range of ?12 V. The SN65175 and SN75175 are designed for optimum performance when used with the SN75172 or SN75174 quadruple differential line drivers. The SN65175 is characterized for operation from -40?C to 85?C. The SN75175 is characterized for operation from 0?C to 70?C.
10.00 AED – 20.00 AED
The SNx4HC595 devices contain an 8-bit, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and serial outputs for cascading. When the output-enable (OE) input is high, the outputs are in the high-impedance state.